The realisation of maps such as log ( ) and antilog ( ) in hardware is presented, due to their importance in several calculating applications. We present an attack to calculate log ( ) and antilog ( ) in hardware. Our attack is based on a tabular array search, followed by an interpolation measure. The interpolation measure is implemented in field programmable gate array ( FPGA ) , consequences an area-efficient, fast design. We perform insertion expeditiously, without the demand to execute generation or division, and our method performs both the log ( ) and antilog ( ) operation utilizing the same hardware architecture. We compare our work with bing methods, and show that our attack consequences in significantly lower memory resource use, for the same estimate mistakes. Besides our method scales really good with an addition in the needed truth, compared to bing techniques.

Keywords- Field-programmable gate arrays ( FPGAs ) , drifting point arithmetic, logarithmic arithmetic, VLSI.

## I. Introduction

THE maps log ( ) and antilog ( ) finds utilizations in many countries such as digital signal processing ( DSP ) , 3-D computing machine artworks, scientific computer science, unreal nervous webs, logarithmic figure systems ( LNS ) , and other multimedia applications. Our attack provides a good solution for field programmable gate array ( FPGA ) -based applications that require high truth with a low cost in footings of required search tabular array ( LUT ) size. Hence, the usage of dedicated hardware to calculate log ( ) and antilog ( ) is

of great value. Two methods those are good researched and used for the coevals of the logarithm map are digit-recurrence algorithms and LUT-based attacks. Out of these methods the digit-recurrence methods are efficient from an country and truth position but have longer latencies

and convergence jobs. The LUT-based methods are widely used to come close the logarithm and antilogarithm maps. LUTs combined with multinomial estimates. The chief aim of all these plants is to use minimal circuit country while retaining the truth of the estimate.

The chief thought of our attack is to utilize LUTs along with additive or quadratic insertion and approximates the generation required for insertion, while calculating a more accurate log ( ) and antilog ( ) . We show that the most cost effectual execution is a LUT with a additive insertion, implemented in a mode that optimizes the country and hold while supplying good truth. Our method is bring forth the logarithm of a figure and besides shows that a similar methodological analysis can be used to bring forth the antilogarithm of a figure. The figure format used is similar to the IEEE 754 individual preciseness drifting point format that has 32 spots. The prima spot is the mark spot, followed by an 8-bit advocate E and a 23 spot mantissa M. The value of a figure X, represented in this format is given by

X=1.m*2E-127, 0 & A ; lt ; m & A ; lt ; 1 ( 1 )

We besides assume that the figure is positive since the logarithm of a negative figure does non be. We target 10 or more spots of truth in this work.

## II. PREVIOUS WORK

The attacks for the approximate the binary logarithm of a figure was given by Mitchell. In his method, the logarithm of a figure is found by attaching the mantissa portion of the figure to the exponent portion. This method is highly easy to implement but gives an absolute mistake every bit high as 0.086 which is merely 3.5 spots of truth. There are assorted writers who have reduced this mistake by utilizing error rectification techniques implemented by simple logic Gatess without affecting generations or divisions. Although these methods are better than Mitchell ‘s attack, they all give less than seven accurate spots Compared to these methods ; our attack is applicable for applications that require a much higher truth. In recent times, most simple maps are generated utilizing LUTs. This attack, ab initio proposed by Brubak involves the calculation of a map utilizing a individual LUT. The truth of the attack depends entirely on the size of the LUT used. Another method improves Brubaker ‘s method by concatenating the lower order spots of the fixed-point part to the value looked up from the tabular array, gives merely a little mistake betterment of one spot. Kmetz proposes to hive away the mistake that occurs due to the Mitchell estimate in the tabular array and add it to the fixed-point part of the figure. This consequences in a farther betterment in mistake ( by3 spots ) with the operating expense of an add operation.

In our attack, we follow the same strategy of hive awaying the mistake values of the Mitchell estimate in a tabular array. Other methods make usage of bigger LUTs to give more accurate consequences, with a good velocity of calculation. We try to happen the optimal table size to utilize for a needed truth. Our attack focuses on utilizing a smaller size tabular array along with a simple additive map to extrapolate between the tabular array values. The chief part of this work is to come close the generation required for the insertion by a method that is fast and consequences in a little mistake. The multipliers in our mark FPGA are restricted to a velocity of 135 MHz, and by avoiding their usage ; we can accomplish much greater velocities, as our consequences indicate. Besides our method lends itself elegantly to execute antilog ( ) operation utilizing the same hardware architecture and truth as log ( ) .

Fig1: mistake due to Mitchell estimate

We show that a good betterment in mistake public presentation can be achieved with the usage of a little LUT and some extra hardware. We compare our consequences with bing methods.

## III. OUR Approach

This work uses a LUT-based attack combined with a additive insertion to bring forth the logarithm of a figure. The generation required in this additive insertion is avoided, ensuing in an country and hold decrease. The thought is described in the undermentioned subdivisions.

A. Interpolation Approach

Mitchell ‘s estimate is given by the undermentioned equation:

Log2 ( 1+ m ) ? m, 0 & A ; lt ; m & A ; lt ; 1 ( 2 )

The mistake due to this estimate is given by:

Em = log2 ( 1+ m ) – m, 0 & A ; lt ; m & A ; lt ; 1 ( 3 )

The mistake curve shown in Fig. 1 is sampled at points ( depending on the size of the LUT required ) . These values are rounded depending on the breadth of the word required and stored in the LUT. The LUT is addressed by the first T spots of the mantissa part of the figure and other staying k-t spots gives the denary value of mantissa part. We investigate the option of extrapolating between the values stored in the tabular array.

This is done by the undermentioned equation:

log2 ( 1+ m ) ? m+a+ ( b-a ) . n1, 0 & A ; lt ; m & A ; lt ; 1 ( 4 )

2k-t

Here m is the mantissa portion, a is the mistake value from the tabular array accessed by the first T spots and B is the following table value adjacent to a. Besides K is the entire figure of MSBs in the fixed-point part used for the insertion and n1 is the denary value of the last k-t spots of the fixed-point part. Here the size of the LUT is 64 word and the breadth of each word is 16 spot. We investigate the instance where a limited figure of insertions are done. We tabulate the maximal mistake incurred when the old algorithm is implemented for T, t+1, and so on until t+8 mantissa spots and disregarding the remainder. This is the same as making different degrees of insertion from 0 to 8.

1 2 3…………………t…………….k

MSB LSB

2t values for LUT Decimal value

Index Stored in k-t spots

We find an mistake value from the tabular array based on the first spots and interpolate between this value and the following value based on the staying spots.

The 3rd term in ( 4 ) requires a generation. In order to besiege the generation ( which is expensive in footings of country and hold ) , we investigate the option of extrapolating repeatedly between any two next values stored in the tabular array. The indispensable thought is that the generation of ( b-a ) and n1 is simplified by taking the antilogarithm of the amount of the logarithm of ( b-a ) and the logarithm of n1. In order to execute this operation with a little hold, we consider the followers options.

1 ) log2 ( b-a ) may be approximated by either of the following two options:

a ) Mitchell estimate ;

B ) LUT: For the LUT option the invariables log2 ( b-a ) for each of the intervals is stored in the original LUT. Remember that we stored the mistake values obtained by utilizing a Mitchell estimate for the log map. The log2 ( b-a ) values are stored along with the mistake values and are indexed by the same reference lines.

2 ) Antilogarithm of ( log2 ( n1 ) + log2 ( b-a ) ) may be approximated by either of the following two options:

a ) Mitchell estimate ;

B ) LUT: To obtain the antilogarithm of a figure by this method, we need to build another LUT. The mistake due to the Mitchell estimate of the antilogarithm map is stored in this LUT. This antilog LUT is utilized to calculate the antilogarithm of a figure, since the generation of ( b-a ) and n1 is performed by taking the antilogarithm of the amount of the logarithm of ( b-a ) and the logarithm of n1.

Fig 2: Block diagram of log engine

Fig 3: Architecture of insertion block

The above figure ( 2 ) shows the block diagram of the log ( ) engine which is basically an execution of ( 4 ) . The architecture of the interpolator block is shown in Fig. 3. Here we merely show the operations on the fixed-point part m. One of the adders is a three input fixed point adder as shown in Fig. 3. It is implemented as 2 adders. Since ( b-a ) takes both negative and positive values for 0 & A ; lt ; m & A ; lt ; 1, the log2 ( b-a ) values stored in the search tabular arraies are really the logarithm of the absolute values of ( b-a ) . It is found that ( b-a ) alterations sign from positive to negative for m & A ; gt ; 0.4427. This is tantamount to comparing the denary value of the first six spots of the fixed-point part with 28, as shown in Fig. 3. Hence, if the first six spots have a value greater than 28, the comparator block sends a control signal to the ADD/SUB block teaching it to execute a subtract operation. The taking one sensor ( LOD ) block is used to happen the log2 ( n1 ) . The LOD detects the first spot that has a value 1.It so uses the staying spots as the fixed-point part part to entree the search tabular array. Since there are 7 spots given as input to the LOD in this illustration, the LOD finds the first place that has a value 1and the staying spots which can be every bit broad as 6 spots is used to entree the LUT. The denary portion of log2 ( n1 ) which is indicated by the place of the first spot with value 1, is straight sent to the three input fixed point adder to be added to the denary portion of log2 ( b-a ) . The end product of the adder after the antilog phase has to be shifted to the right or left depending on the denary end product of the fixed point adder. Besides there is a 27 term in the denominator of ( 4 ) and this is accounted for by a changeless right displacement of 7 spots at the end product of the adder of the antilog LUT. In Fig. 3, the blocks stand foring a LUT for log2 ( b-a ) and a LUT for log2 ( n1 ) are indistinguishable and can be implemented utilizing a double port RAM. Besides note that, the reference of each of the three LUTs shown in Fig.3 has a breadth of 6 spots. In each instance the 6 spot address word is obtained by rounding off the value of the following LSB in the word from which the reference word is derived. The unit of ammunition ( ) operation is implemented utilizing an adder. All the measures that are rounded off in this mode are annotated as such in fig 3.

## IV. Application

The followers are the most of import applications of logarithmic ( ) calculations.

The calculations of log ( ) and antilog ( ) are uses in many countries such as digital signal processing ( DSP ) , 3-D computing machine artworks, scientific computer science, unreal nervous webs, logarithmic figure systems ( LNS ) , and other multimedia applications.

It provides a good solution for field programmable gate array ( FPGA ) -based applications that require high truth with a low cost in footings of required search tabular array ( LUT ) size.

It gives more accurate consequence up to 10 spots in fractional portion without demand to execute generation and division operation.

Its gives country efficient and fast design without hold.

## V. CONCLUSION

The execution of maps such as log ( ) and antilog ( ) in hardware is of import, due to their prevalence in several calculating applications. In this paper, we present an attack to calculate log ( ) and antilog ( ) in hardware. Our attack is based on a LUT, followed by an interpolation measure. The freshness of our attack lies in the fact that we find the log ( ) of a figure expeditiously utilizing insertion, without the demand to explicitly execute generation or division. While calculating the logarithm of a figure, we perform the generation required during the interpolation measure, by using an antilogarithm operation. The antilogarithm operation is besides performed by using a LUT. We compare our work with bing methods, and show that our attack consequences in significantly lower memory use for the same truth. Besides our method scales highly good to suit higher truths. One interesting add-on to our method would be to research the usage of LUTs of sizes other than powers of 2. This will give our method more scalability.